1. Field of the Invention
The invention relates to a waveform shaping circuit which is used in a code transmitting apparatus.
2. Description of the Related Art
An important component element in a digital code transmitting apparatus is a waveform shaping circuit (hereinafter, referred to as a xe2x80x9cNyquist filterxe2x80x9d) for data transmission. In the shaping circuit, in a frequency domain of a signal, an attenuation in a stop band is set to an equal ripple, and in a time domain of a signal, an inter-symbol interference is approximated to xe2x80x9c0xe2x80x9d.
A construction of a conventional digital Nyquist filter is shown in a block diagram of FIG. 1.
Construction of the digital Nyquist filter will be described hereinbelow with reference to FIG. 1.
First, a symbol rate signal generator 1 is a circuit for generating a symbol rate signal by frequency dividing a clock signal serving as a reference of the operation of the digital Nyquist filter. The symbol rate signal denotes a signal synchronized with a symbol frequency of an input signal. Generally, when an analog/digital converter, which will be explained hereinlater, executes what is called an xe2x80x9coversamplingxe2x80x9d operation, a frequency of the clock signal is equal to a value that is an integer times of a symbol rate (symbol frequency). In an example of the circuit shown in FIG. 1, it is assumed that the symbol rate is set to 1 Hz, and the frequency of the clock signal is set to 3 Hz. An oversampling number M in this case is defined as follows.
M=(clock signal frequency)/(symbol frequency)=3 
An analog/digital converter (hereinafter, simply abbreviated to xe2x80x9cADCxe2x80x9d) 2 is a circuit for quantization converting a supplied analog signal into a digital signal comprising a predetermined number of bits such as 8 bits or 16 bits. Therefore, digital signals according to the number of bits are generated from the ADC 2. That is, circuits subsequent to an impulse generator 3 are provided for every bit of a digital conversion output from the ADC 2.
The impulse generator 3 is a circuit for converting the digital conversion output from the ADC 2 which changes at the symbol rate of the input signal, into an impulse-shaped signal which changes at the frequency of the clock signal.
A delay element 4 is a circuit for providing a delay synchronized with the sampling clock for the impulse-shaped signal. A coefficient multiplier 5 is a circuit for multiplying an output of a tap of each delay element 4 by a predetermined filtering coefficient for every tap. An adder 6 is a circuit for adding outputs from the coefficient multipliers 5 of the taps.
Subsequently, the operation of the digital Nyquist filter shown in FIG. 1 will be described hereinbelow.
First, an analog input signal is converted into a predetermined digital signal by the ADC 2. The ADC 2 executes the analog/digital converting operation by a clock signal whose sampling rate is equal to 3 Hz. However, a symbol rate signal of 1 Hz is supplied to an enable terminal which permits the output of the circuit. Therefore, the digital output from the ADC 2 changes synchronously with the symbol rate.
The digital output from the ADC 2 is subsequently supplied to the impulse generator 3, and converted into an impulse train synchronized with the clock signal of 3 Hz. A state of an input signal Sj in the impulse generator 3 is shown in a time chart of FIG. 2A. A state of an output signal Xn is shown in a time chart of FIG. 2B. In FIG. 2, in order to make understanding easy, each of the input and output signals is shown by amplitude values quantized to seven levels in a range from +3 to xe2x88x923 including 0. Each of the actual input and output of the impulse generator 3 is a signal at a logic level obtained by encoding the amplitude value by a predetermined number of bits. The signal at the logic level here is a signal in which each of the encoded bits is expressed by xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
Assuming that, an output of the circuit shown in FIG. 1 is set to Yn, since Yn is a summation of signals which passed through the taps of the digital filter shown in the diagram, it can be expressed in a form as shown by the following equation (1).                                                                         Y                n                            =                                                                    C                                          1                      ,                      0                                                        ⁢                                      X                    n                                                  +                                                      C                                          1                      ,                      1                                                        ⁢                                      X                                          n                      -                      1                                                                      +                                                      C                                          1                      ,                      2                                                        ⁢                                      X                                          n                      -                      2                                                                      +                                                      C                                          2                      ,                      0                                                        ⁢                                      X                                          n                      -                      3                                                                      +                                                      C                                          2                      ,                      1                                                        ⁢                                      X                                          n                      -                      4                                                                      +                                                      C                                          2                      ,                      2                                                        ⁢                                      X                                          n                      -                      5                                                                                                                                              =                                                ∑                                                            C                                              1                        ,                        k                                                              ⁢                                          X                                              n                        -                        k                                                                                            +                                                      C                                          2                      ,                      k                                                        ⁢                                      X                                          n                      -                      k                      -                      3                                                                                                                              (        1        )            
(where, a sum signal xe2x80x9cxcexa3xe2x80x9d in the equation expresses the summation in a range from k=0 to 2 with respect to a suffix k. It is defined that xe2x80x9cxcexa3xe2x80x9d in the mathematical expressions disclosed in the following description has a meaning similar to that mentioned above.)
In the equation (1), n denotes an integer and has a value to which +1 is added every sampling period of the clock signal. Coefficients C1,0 to C2,2 are filtering coefficients which have been predetermined for the coefficient multipliers 5 shown in FIG. 1, respectively.
Signals Xi (Xn to Xnxe2x88x925) of the respective taps in the digital filter in FIG. 1 can be expressed by the following equations, as will be obviously understood from the time chart of FIG. 2B.
Xi=Xi(i mod 3=0),Xi=0(i mod 3xe2x89xa00)xe2x80x83xe2x80x83(2) 
where, xe2x80x9cmodxe2x80x9d (modulo) is an operator which is used to classify the whole integer by a remainder of a division. That is, xe2x80x9ci mod 3xe2x80x9d denotes that an integer i is classified into three groups by remainders 0, 1, and 2 which are obtained when the integer i is divided by 3.
That is, the equations (2) denote the following meaning. Only when the remainder which is obtained by dividing the suffix i of the signal Xi by 3 is equal to 0 (for example, X0, X3, X6, . . . in FIG. 2B), Xi=Xi. When the remainder is equal to 1 or 2 (for example, X1, X2, X4, . . . in FIG. 2B), Xi=0.
Subsequently, consideration is given to a suffix (nxe2x88x92k) of X in the first term of the right side in the equation (1). Since k can have only three values 0, 1, and 2, it is assumed that k=n mod 3. By substituting k =n mod 3 into the suffix (nxe2x88x92k) of X of the first term of the right side in the equation (1), (nxe2x88x92k) is expressed by the following equation (3).
nxe2x88x92k=nxe2x88x92(n mod 3)xe2x80x83xe2x80x83(3) 
Further, a remainder which is obtained by dividing the equation (3) by 3 becomes as follows.
(nxe2x88x92k) mod 3=(nxe2x88x92(n mod 3)) mod 3=0 
The equation is a calculation such that a value obtained by subtracting a remainder obtained by dividing n by 3 from the integer n is further divided by 3 and a resultant remainder is obtained. A result of the calculation is, therefore, equal to 0.
From those results and the conditions of the equations (2), only when k=n mod 3, Xnxe2x88x92k=Xnxe2x88x92k. In cases other than the case where k=n mod 3, Xnxe2x88x92k=0. The first term of the right side of the equation (1), therefore, can be simplified as follows.
xcexa3C1,kXnxe2x88x92k=C1,(n mod 3)Xnxe2x88x92(n mod 3)xe2x80x83xe2x80x83(4) 
Now, consideration is given to the input/output signals of the impulse generator 3 in FIG. 1. As will be understood from FIG. 2A or 2B, only the input signal at the time when the output is X0, X3, X6, . . . is meaningful. An output signal X in the equation (4) can be expressed as follows by using an input signal S.
Xnxe2x88x92(n mod 3)=Sjxe2x80x83xe2x80x83(5) 
where, J is an integer and a value which is increased by +1 every 1 symbol period.
By substituting the equation (5) into the equation (4), the first term of the right side of the equation (1) can be expressed as follows.
xcexa3C1,kXnxe2x88x92k=C1,(n mod 3)Sjxe2x80x83xe2x80x83(6) 
Subsequently, consideration is given to a suffix (nxe2x88x92kxe2x88x923) of X with respect to the second term of the right side of the equation (1). Also in this case, assuming that k=n mod 3 in a manner similar to the case of the first term, the suffix can be expressed as follows.
nxe2x88x92kxe2x88x923=nxe2x88x92(n mod 3)xe2x88x923 
By using a remainder which is obtained by dividing it by 3, the following equation is obtained.
(nxe2x88x92kxe2x88x923) mode 3=(nxe2x88x92(n mod 3)xe2x88x923) mod 3=0 
By the conditions of the equations (2), only when k=n mod 3,
Xnxe2x88x92kxe2x88x923=Xnxe2x88x92kxe2x88x923 
When kxe2x89xa0n mod 3,
Xnxe2x88x92kxe2x88x923=0 
The second term of the right side of the equation (1) can be simplified as follows in a manner similar to the first term of the right side.
xcexa3C2,kXnxe2x88x92kxe2x88x923=C2,(n mod 3)Xnxe2x88x92(n mod 3)xe2x88x923xe2x80x83xe2x80x83(7) 
If the output signal X is expressed by the input signal S of the impulse generator 3 in FIG. 1, the following equation is obtained.
Xnxe2x88x92(n mod 3)xe2x88x923=Sjxe2x88x921xe2x80x83xe2x80x83(8) 
The second term of the right side of the equation (1) can be, therefore, expressed as follows by the equations (7) and (8).
xcexa3C2,kXnxe2x88x92kxe2x88x923=C2,(n mod 3)Sjxe2x88x921xe2x80x83xe2x80x83(9) 
From those results, the equation (1) showing the output signal Yn can be simplified as follows by the equations (6) and (9).
Yn=C1,(n mod 3)Sj+C2,(n mod 3)Sjxe2x88x921xe2x80x83xe2x80x83(10) 
The output signal Yn is supplied to a digital/analog converter (not shown) as necessary, and becomes an analog signal subjected to a waveform shaping process.
In the circuit shown in FIG. 1, filtering characteristics of a desired order can be achieved by setting a value of the number N of taps of the filter (N=6 in the circuit of FIG. 1), and values of the filtering coefficients C1,0 to C2,2 to proper numerical values, respectively.
In the digital Nyquist filter, there is a problem that, if the filtering characteristics are complicated and are set to a high order, the number of taps increases and the scale of the circuit is substantially increased. There is also a problem that in association with an increase in circuit scale, the summation of delay times which are due to delay elements and coefficient multipliers included in the circuit increases, and an operating speed of the filter decreases.
The invention is intended to overcome the above-discussed problems, and it is an object of the invention to provide a digital Nyquist filter in which a circuit scale is small and an operating speed is high.
According to the invention, there is provided a waveform shaping circuit for sampling an analog input signal and performing a waveform shaping process, comprising:
an analog/digital converting circuit for sampling the input signal on the basis of a sampling clock, thereby digitizing it; at least one delay circuit for providing a delay synchronized with a symbol rate of the input signal for an output signal of the analog/digital converting circuit; a coefficient selecting circuit for sequentially selecting one of a plurality of predetermined characteristics values synchronously with the sampling clock and setting the selected characteristics value to a predetermined coefficient; a multiplying circuit for multiplying each of an input signal and an output signal of the delay circuit by the predetermined coefficient, thereby obtaining at least two multiplication outputs; and an adding circuit for adding the multiplication outputs.